Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics

verfasst von: Muhammad Fahlesa Fatahilah, Feng Yu, Klaas Strempel, Friedhard Römer, Dario Maradan, Matteo Meneghini, Andrey Bakin, Frank Hohls, Hans Werner Schumacher, Bernd Witzigmann, Andreas Waag, Hutomo Suryo Wasisto
Abstract: This paper reports on the direct qualitative and quantitative performance comparisons of the field-effect transistors (FETs) based on vertical gallium nitride nanowires (GaN NWs) with different NW numbers (i.e., 1–100) and diameters (i.e., 220–640 nm) fabricated on the same wafer substrate to prove the feasibility of employing the vertical 3D architecture concept towards massively parallel electronic integration, particularly for logic circuitry and metrological applications. A top-down approach combining both inductively coupled plasma dry reactive ion etching (ICP-DRIE) and wet chemical etching is applied in the realization of vertically aligned GaN NWs on metalorganic vapor-phase epitaxy (MOVPE)-based GaN thin films with specific doping profiles. The FETs are fabricated involving a stack of n-p-n GaN layers with embedded inverted p-channel, top drain bridging contact, and wrap-around gating technology. From the electrical characterization of the integrated NWs, a threshold voltage (V_th) of (6.6 ± 0.3) V is obtained, which is sufficient for safely operating these devices in an enhancement mode (E-mode). Aluminium oxide (Al₂O₃) grown by atomic layer deposition (ALD) is used as the gate dielectric material resulting in nearly-zero gate hysteresis (i.e., forward and backward sweep V_th shift (ΔV_th) of ~0.2 V). Regardless of the required device processing optimization for having better linearity profile, the upscaling capability of the devices from single NW to NW array in terms of the produced currents could already be demonstrated. Thus, the presented concept is expected to bridge the nanoworld into the macroscopic world, and subsequently paves the way to the realization of innovative large-scale vertical GaN nanoelectronics.
Externe Organisation(en): Technische Universität Braunschweig
Universität Kassel
Physikalisch-Technische Bundesanstalt (PTB)
Università degli Studi di Padova
Typ: Artikel
Journal: Scientific reports
Band: 9
ISSN: 2045-2322
Publikationsdatum: 01.12.2019
Publikationsstatus: Veröffentlicht
Peer-reviewed: Ja
ASJC Scopus Sachgebiete: Allgemein
Elektronische Version(en): https://doi.org/10.1038/s41598-019-46186-9 (Zugang: Offen)

BibTeX

@article{7fef4402454d4b6e8fbbb25001062cf8,
title = "Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics",
abstract = "This paper reports on the direct qualitative and quantitative performance comparisons of the field-effect transistors (FETs) based on vertical gallium nitride nanowires (GaN NWs) with different NW numbers (i.e., 1–100) and diameters (i.e., 220–640 nm) fabricated on the same wafer substrate to prove the feasibility of employing the vertical 3D architecture concept towards massively parallel electronic integration, particularly for logic circuitry and metrological applications. A top-down approach combining both inductively coupled plasma dry reactive ion etching (ICP-DRIE) and wet chemical etching is applied in the realization of vertically aligned GaN NWs on metalorganic vapor-phase epitaxy (MOVPE)-based GaN thin films with specific doping profiles. The FETs are fabricated involving a stack of n-p-n GaN layers with embedded inverted p-channel, top drain bridging contact, and wrap-around gating technology. From the electrical characterization of the integrated NWs, a threshold voltage (Vth) of (6.6 ± 0.3) V is obtained, which is sufficient for safely operating these devices in an enhancement mode (E-mode). Aluminium oxide (Al2O3) grown by atomic layer deposition (ALD) is used as the gate dielectric material resulting in nearly-zero gate hysteresis (i.e., forward and backward sweep Vth shift (ΔVth) of ~0.2 V). Regardless of the required device processing optimization for having better linearity profile, the upscaling capability of the devices from single NW to NW array in terms of the produced currents could already be demonstrated. Thus, the presented concept is expected to bridge the nanoworld into the macroscopic world, and subsequently paves the way to the realization of innovative large-scale vertical GaN nanoelectronics.",
author = "Fatahilah, {Muhammad Fahlesa} and Feng Yu and Klaas Strempel and Friedhard R{\"o}mer and Dario Maradan and Matteo Meneghini and Andrey Bakin and Frank Hohls and Schumacher, {Hans Werner} and Bernd Witzigmann and Andreas Waag and Wasisto, {Hutomo Suryo}",
note = "Funding information: The authors would like to thank A. Schmidt, J. Breitfelder, M. R{\"u}hmann, and K.-H. Lachmund for their valuable technical assistances. Authors are also grateful for the planar GaN wafers provided by the members of epitaxy competence center (ec2) of TU Braunschweig (I. Manglano Clavero and C. Margenfeld). This work has been performed within the projects of {\textquoteleft}LENA-OptoSense{\textquoteright} funded by the Lower Saxony Ministry for Science and Culture (MWK) and {\textquoteleft}3D Concepts for Gallium-Nitride Electronics (3D GaN){\textquoteright} funded by the German Research Foundation (DFG). Support by Ministry of Research, Technology, and Higher Education of the Republic of Indonesia (RISTEKDIKTI) and Indonesian-German Center for Nano and Quantum Technologies (IG-Nano) is also acknowledged. The research activity at University of Padova was partly funded by project “Novel vertical GaN-devices for next generation power conversion”, NoveGaN (University of Padova), through the STARS CoG Grants call.",
year = "2019",
month = dec,
day = "1",
doi = "10.1038/s41598-019-46186-9",
language = "English",
volume = "9",
journal = "Scientific reports",
issn = "2045-2322",
publisher = "Nature Publishing Group",
number = "1",
}